Events
Midtem exams startedMidterm exams endedCompleted testing the various unitsPresented mid term progressDesigned the datapathCreated the remaining modulesCreated the testbenchTested the entire codeStarted BrainstormingCompleted the basic design idea.Started with verilog!Started coding the processor.Desinged the ISA.Designed various components (except Datapath)Event progress
Project startedProject almost completed, still a long way to go!
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