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CSN221
Created by
swapnil negi
⟶ Updated 6 Nov 2017 ⟶
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Events
Midtem exams started
Midterm exams ended
Completed testing the various units
Presented mid term progress
Designed the datapath
Created the remaining modules
Created the testbench
Tested the entire code
Started Brainstorming
Completed the basic design idea.
Started with verilog!
Started coding the processor.
Desinged the ISA.
Designed various components (except Datapath)
Event progress
Project started
Project almost completed, still a long way to go!
